Received 02.01.2026, Revised 13.05.2026, Accepted 25.06.2026 Published 03.08.2026

Parallelism and WebAssembly memory management in microinterface architecture

Oleksandr Stepanov*, Halyna Klym

oleksandr.v.stepanov@lpnu.ua



The decentralisation of monolithic front-ends into micro-front-end architectures, combined with WebAssembly (Wasm), imposes limitations on the communication overhead associated with ‘bridge crossing’ between JavaScript and Wasm’s linear memory, an area that remains under-researched in quantitative terms. The aim of the study was to quantitatively assess the overhead of bridge crossing, analyse the risks of race conditions in shared-memory micro-frontend environments, and develop and validate a hybrid communication model that eliminates serialisation bottlenecks. A controlled micro-benchmark methodology was employed for the study, utilising the browser API performance.now() with a measurement precision of no less than 5 microseconds. Each scenario was run over 10,000 measurement iterations following a mandatory JIT compiler warm-up phase of 1,000 iterations. Two architecturally distinct data transfer strategies were compared under identical hardware conditions using Float32Array arrays ranging in size from 0.1  MB to 10  MB at a rendering rate of 60 frames per second. It has been empirically established that the transfer of primitive data types takes 50-100 nanoseconds, whereas copying large data arrays (e.g., 1 MB) takes 1-3 milliseconds – which, at a frame rate of 60 frames per second, consumes 11.1% of available CPU time solely on data transfer, completely negating Wasm’s performance advantages. The proposed hybrid model, which combines a lightweight event bus for transmitting control signals with a SharedArrayBuffer and Atomics-based synchronisation for data access, achieves a transaction time of 250 nanoseconds regardless of payload size – corresponding to a speed-up factor of up to 66,000 times for 10 MB arrays compared to classical event-driven communication. The results provided a quantitatively validated architectural foundation for designing high-performance loosely coupled micro-frontend systems capable of performing AI/ML inference, 3D rendering and video streaming directly within the browser without architectural compromises

Wasm technology; micro-frontends; SharedArrayBuffer; data transfer strategies; event bus; Atomics; overhead
121-131
Stepanov, O., & Klym, H. (2026). Parallelism and WebAssembly memory management in microinterface architecture. Information Technologies and Computer Engineering, 23(2), 121-131. https://doi.org/10.31649/vitce/2.2026.121

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