Received 18.08.2013, Revised 30.10.2013, Accepted 10.12.2013

Features of the architecture and structure of reconfigurable graphics accelerators

Yuriy Yakovlev

Features of construction of accelerators with reconfiguration by usage are observed: diagrammes of connections for sampling of optimal resources of the accelerator; scalings of system at the expense of usage of the updated ring bus; applications the PLIS for an accelerator pattern under type of the solved task; architectures of type "processor-in-memory" with application of the offered method of allocation of the graphics task on system processors. Thus offered is architectural-structural solutions are protected by patents of Ukraine

reconfiguration, the accelerator, the "processor-in-memory", the programmed logical chip (PLC)
26-36
Yakovlev, Yu. (2013). Features of the architecture and structure of reconfigurable graphics accelerators. Information Technologies and Computer Engineering, 10(3), 26-36.

References

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