Synthesis of a control device based on r-automaton for associative processor
Tatiana Martyniuk, Bohdan Krukivskyi, Serhii Bohomolov, Aryna KuzinaThis article discusses one of the well-known options for the synthesis of control devices with rigid logic. Such control devices provide a significant response speed compared to control devices with programmable logic, but they have a laborious process at the stages of abstract and structural synthesis of a microprogram automaton (MPA) as the basic structural model of this type of control device. Synthesis of an MPA based on a shift register as an R-automaton provides a compromise solution among the implementations of an MPA based on a parallel register as a T-automaton or a counter as a CT-automaton. This is due to the load on the memory of the MPA by reducing the complexity of the logical part of the MPA, namely its combinational scheme. The use of a specific single positional coding of the MPA states makes it possible to significantly simplify the complex process of the formation of Boolean functions corresponding to the excitation functions in the abstract synthesis of the MPA. And this, in turn, leads to a simplification of the combinational part of the MPA. At the same time, the complication of the memory part of the MPA based on the shift register leads to an increase in its bit rate without reducing the regularity of its structure. The article proposes a non-standard approach to the synthesis of a control device and develops its functional scheme. As a result, synthesis on the basis of the R - automaton of the control device structure for the associative processor confirmed the perspective of this version of MPA synthesis by simplifying the process of the corresponding abstract and structural synthesis. This is due to the simplicity of forming direct and simplified structural tables using single positional coding of MPA states. It is planned to place the developed structure of the control device in a programmable logic IC (FPGA), which will allow the placement of the entire associative processor in the FPGA. This approach will ensure the compactness of the organization and the speed of the associative processor
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